1. Field of the Invention
The invention generally relates to electronics, and in particular, to non-return-to-zero (NRZ) serializer-deserializer (SerDes) communication devices.
2. Description of the Related Art
In SerDes communication, one of the primary design considerations is the tolerance of the receiver to jitter. This jitter can take many forms: random with Gaussian distribution, bounded uncorrelated, bounded correlated, sinusoidal, duty cycle distortion, etc.
A receiver that is more tolerant to jitter has a great advantage as the SerDes link can then operate over greater distances and/or over poorer channels. Numerous techniques exist for improving SerDes receiver jitter tolerance in the presence of signal impairments. These techniques range from very sophisticated techniques that provide substantial jitter tolerance improvement, but at the cost of high receiver complexity, to simple techniques that provide only minimal jitter tolerance improvement.
The use of signal equalization and/or pre-conditioning is a common approach. Equalization can be performed in the analog domain, or in the digital domain following sampling of the received signal with an Analog-to-Digital Converter (ADC). Equalization can be linear or non-linear in nature. Using equalization, data correlated impairments are reduced, providing more tolerance to jitter. Examples can be found in, for example, U.S. Pat. Nos. 6,088,415; 5,452,333; and 6,765,975.
For SerDes signals that are distorted primarily by Duty Cycle Distortion, a common approach is to offset the decision level of the slicer. Examples using this basic technique can be found in, for example, U.S. Pat. No. 4,736,391, and U.S. Patent Application Publication Nos. 2007/0297548 and 2006/0203939.
For SerDes signals that are distorted primarily by Duty Cycle Distortion, another common approach is to adjust the average timing phase based on the estimated signal duty cycle. Examples using this basic technique can be found in U.S. Pat. No. 5,761,254 and in U.S. Patent Application Publication No. 2004/0062336.
Yet another technique for accommodating Duty Cycle Distortion is to adjust the duty cycle of the local clock based on the duty cycle of the incoming data as disclosed in, for example: U.S. Pat. No. 7,298,807.
When attempting to operate over greater distances and/or poorer channels, Inter-Symbol Interference (ISI) often becomes a dominating factor in jitter tolerance. In the context of SerDes, ISI is often referred to as Data Dependent Jitter (DDJ). Most often, ISI is the result of a low-pass frequency response of the transmission channel medium. That is, the low frequency portion of the transmitted waveform is more easily passed, while the higher frequency portion of the transmitted waveform tends to be attenuated in amplitude. To those skilled in the art, the impact on the transmitted “eye” of the signal is well known. Typically, horizontal and vertical opening of the “eye” becomes smaller with increasing levels of ISI.
FIG. 1 illustrates two different exemplary eye diagrams. Both diagrams show eight different signal path trajectories, corresponding to the eight possible combinations of three sequential binary digits: 000, 001, 010, 011, 100, 101, 110, 111. The first eye diagram (to the left) depicts an ideal case, in which the eye is maximally open in both the vertical and horizontal direction. In this case, there is no ISI and the eight different trajectories are hard to differentiate. The second eye diagram (to the right) depicts the case in which significant ISI has distorted the signal and the eight different signal trajectories are clearly visible. Also, in both eye diagrams, the eye opening is shown by a diamond. Clearly, the eye opening in the ideal case is larger.
In the ideal channel example, the timing of the data decision moment can be offset from ideal by as much as one-half the baud period before a data decision error is made. However, in the case of the ISI channel, the amount of offset from ideal that can be tolerated is less than one-half of a baud period. This reduction results in a reduction of the jitter tolerance.
There several common methods to address the described problem. If the received signal is sampled with a multi-level ADC, then it is possible to apply a digital equalizer to compensate for the ISI, thus opening the effect “eye” of the signal and improving jitter tolerance.
Similarly, it is possible to implement an equalizer in analog circuitry. The analog approach removes the need for a multi-level ADC, but has its own set of complications.
Yet another possible design approach to address the problem is to perform pulse extension. This can be done in either the analog domain or in the digital domain.
FIG. 2 and FIG. 3 illustrate the operation of a conventional asynchronous SerDes receiver. Numerous variations exist for this basic structure; however, this basic structure will serve to illustrate the problem at hand.
In FIG. 2, the receiver samples the received NRZ waveform multiple times per baud period using a 1-bit ADC (that is, a “slicer”) 202. The sampling rate provided by the sample clock is approximately equal to an integer multiple of the baud rate. N consecutive samples are collected and output by the SIPO (Serial In, Parallel Out) block 204 at a correspondingly lower rate. A lower rate clock signal is also provided by a divide by N block 210, which divides the sample clock by N. From each group of samples, the Sample Selection block 206 selects and outputs the 1-bit sample corresponding to the center of the baud period and the sample offset from this sample by ½ of the baud period. The first 1-bit sample is the recovered NRZ data bit. The second 1-bit sample helps with timing recovery, for example, when using the Gardner algorithm. The Timing Control block 208, which implements the Gardner algorithm or other suitable timing recovery technique, is responsible for determining the correct timing and communicating to the Sample Selection block 206 which samples to select. Due to the asynchronous nature of the receiver, it is possible that some sample groups do not contain a data sample while other sample groups contain two data samples. These are issues familiar to those knowledgeable in the art and do not need to be discussed in detail.
FIG. 3 illustrates the signal sampling process and the selection of the Data sample and the additional sample for timing control purposes. In this example, samples of the received waveform are taken at a frequency that is 8 times the approximate baud rate. That is, there are approximately 8 samples per baud. When the received waveform is greater than or equal to the slicer threshold, a “1” is output by the slicer 202 (FIG. 2). When the received waveform is less than the slicer threshold, a “0” is output by the slicer 202. Eight consecutive samples are grouped by the SIPO block 204. Of these eight samples, one sample is identified to be the timing sample 220 (FIG. 2) and one sample is identified to be the data sample 222 (FIG. 2). In the described asynchronous receiver, the selection of the data sample 222 is very simple and is sensitive to the problem with isolated pulses described earlier.